The present invention concerns a semiconductor memory device, and particularly a dynamic random access memory (RAM) having improved write function.
In a dynamic RAM, data stored in a memory cell selected by an address are loaded as a voltage on a bit line, while a charge stored in a dummy cell (or pre-charge voltage) is loaded on a complementary bit line as a reference voltage with respect to the voltage of the bit line. The voltage difference between the bit line and the complementary bit line is sufficiently amplified by a sense amplifier, etc., and then read out through input/output lines and a data output buffer. In addition to above the read function, the dynamic RAM performs write function for storing data in a memory cell selected by an address. During the write function, the potentials of the bit line lines are determined by the potential of data supplied through a data input buffer. Such dynamic RAM performing the read/write function is disclosed in the known technical references, and FIG. 1A shows a typical column circuit of such a conventional dynamic RAM.
Referring to FIGS. 1A and 1B, FIG. 1A illustrates the column circuit and FIG. 1B illustrates operational timing diagrams according to FIG. 1A. A bit line equalization circuit 10 connected to a bit line pre-charge voltage V.sub.BL of the level (1/2)VCC equalizes a pair of bit lines BL and BL into the level of (1/2)Vcc in response to an equalization signal EQ, during a row address strobe signal RAS being pre-charged at "high" state. On the other hand, the equalization signal EQ is disabled and a memory cell 20 connected to a word line WL is selected, during the RAS being active at "low" state. Then, the charge stored in the memory cell 20 is discharged to the bit line BL, and the charge stored in a dummy cell which is not shown is discharged to the complementary bit line BL (or maintaining the pre-charged level). Thereafter, as a sense amplifier 30 including two PMOS transistors and two NMOS transistors is operated according to sensing clock pulses LA and LA, the voltage difference between the bit line BL and the complementary bit line BL is more amplified. The amplified data R1 is delivered to a pair of input/output lines IO and IO, through a column gate 50 driven in response to a column selection signal CSL which is enabled according to a column address strobe signal CAS. The input/output lines are generally equalized to a higher level which is, for example, dropped by the threshold voltage of the MOS transistor from the source voltage Vcc, than the equalization level of the bit lines. After reading out the data R1, the bit lines are again equalized by the equalization signal EQ. Then, when a new read data R2 is read out in like manner and a write enabling signal WE activated, the potential of the bit line pair BL, BL is determined according write data W which is externally supplied thereto. Normally, the potential difference of the bit line pair is substantially identical to the source voltage level. In the event that the bit lines are connected to the input/output lines through the column gate 50 which is turned on by the column selection signal CSL at "high" state, the potentials on the bit line BL and the complementary bit line BL are then transmitted. Hence, a considerable transition time is required until the input data on the input/output lines is sufficiently transferred to the bit lines, thus resulting in an undesirable delay of the writing time.
When the potentials of the bit lines have the swinging width as much as the source voltage level during the read-write transition, as in prior art, noises are produced in response to the swing width. Furthermore, since the self-resistance of the long bit lines in a high integrated memory device is higher, an influence according to noises is increased.